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[VHDL-FPGA-VerilogAvalon_PWM_IP_pwm

Description: Avalon总线下的PWM的IP模块。基于VHDL语言。-Avalon Bus IP of the PWM module. Based on the VHDL language.
Platform: | Size: 20480 | Author: 李超 | Hits:

[VHDL-FPGA-Verilogpwm__vhdl

Description: 一个基于vhdl语言的脉冲宽度调制。并且有两个脉冲输出-Vhdl language-based pulse width modulation. And two pulse output
Platform: | Size: 904192 | Author: 邹细男 | Hits:

[VHDL-FPGA-VerilogEP1C3_12_1_2_MOTO

Description: 基于FPGA的直流电机的PWM控制和步进电机的细分驱动控制。使用VHDL语言编写,压缩包里是Quartus下的工程。-FPGA-based PWM DC motor control and stepper motor-driven control of a breakdown. The use of VHDL language, compression bag is under the Quartus project.
Platform: | Size: 1193984 | Author: deadtomb | Hits:

[Industry researchpwm

Description: counter for pwm in order to generate pulses for the module it is required to write a program for counter
Platform: | Size: 2048 | Author: penguin | Hits:

[VHDL-FPGA-VerilogPulse_Width_Modulator_Altera_MAX_II_CPLD_Design_E

Description: Example VHDL project showing how to use a PWM by CPLD
Platform: | Size: 290816 | Author: maros | Hits:

[VHDL-FPGA-Verilogpmw2ppm

Description: Vhdl code PPM to pwm converte
Platform: | Size: 4096 | Author: SANTOSH | Hits:

[VHDL-FPGA-VerilogADC0809

Description: 完整ADC0809的时序,采用VHDL语言编写,在Altera cycloneI/II系列下的EP1C6\EP2C5\8平台下测试完成,稳定-ADC0809 Driver by VHDL
Platform: | Size: 406528 | Author: ziyan | Hits:

[VHDL-FPGA-VerilogPWMtest

Description: PWM 转模拟信号 拨码开关控制 PWM 的占空比为16级,分别对应电压3.3伏16分之一的倍数-DIP switch to an analog signal PWM switch control PWM duty cycle is 16, corresponding to voltage of 3.3 volts, one of the 16 sub-multiples
Platform: | Size: 140288 | Author: panda | Hits:

[VHDL-FPGA-VerilogPWM-OUT

Description: 这里是一个比较好的用Verilog写的通过按键控制PWM输出从而控制小灯亮灭程度的经典例子~!~-Here is a better written in Verilog by using buttons to control the PWM output level of the control of small lights eliminate the classic example of ~! ~
Platform: | Size: 311296 | Author: ll | Hits:

[VHDL-FPGA-Verilogcomponents

Description: quartus的几个IP核(PWM,RAM,I2C)-quartus several IP core (PWM, RAM, I2C)
Platform: | Size: 226304 | Author: 宋瑞 | Hits:

[VHDL-FPGA-Verilogfpga-pwm

Description: 用verilog 语言写的FPGA子程序,环境是quartus II 7.2 已经在EP1C6Q240上测试过,源码包含仿真文件和仿真结果,本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines.
Platform: | Size: 1163264 | Author: 黄家武 | Hits:

[MultiLanguagefinal

Description: nice control program pwm
Platform: | Size: 892928 | Author: adhominen | Hits:

[VHDL-FPGA-VerilogVGAPWM

Description: FPGA PWM control and VGA display use VHDL language with simulation.
Platform: | Size: 309248 | Author: xiaominjin | Hits:

[VHDL-FPGA-Verilogpwm

Description: vhdl model for a 3 phase system
Platform: | Size: 2048 | Author: dante | Hits:

[OtherPWM_GEN

Description: 这是Altera PWM生成的一个实例。包含project文件,源代码,仿真文件。经过验证,实际可用。-This is an example of Altera PWM generated. Contains the project files, source code, simulation files. After verification, the actual available.
Platform: | Size: 250880 | Author: 洛空奇 | Hits:

[Windows DevelopPWM

Description: PWM generator made in VHDL
Platform: | Size: 2048 | Author: pumaju | Hits:

[VHDL-FPGA-VerilogPWM

Description: it is a program for producing PWM signals to control a motor
Platform: | Size: 156672 | Author: mohsen | Hits:

[VHDL-FPGA-Verilogan501_design_example

Description: 在MAX2系列CPLD上实现脉冲宽度调制(PWM),完整的设计成程序和仿真结果。-In the MAX2 series CPLD to realize pulse width modulation (PWM), a complete design and simulation results into the program.
Platform: | Size: 259072 | Author: 王志慧 | Hits:

[VHDL-FPGA-Verilogpwm

Description: 采用VHDL编写的步进电机控制程序。运行200步后停止-Prepared using VHDL stepper motor control program. After running 200 steps to stop
Platform: | Size: 3072 | Author: 邓志远 | Hits:

[VHDL-FPGA-Verilogpwm

Description: 用VHDL语言 描述 生成pwm的 IP核-Pwm using VHDL language to describe the generation of IP core
Platform: | Size: 1024 | Author: chong | Hits:
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